TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 779

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31:11]
[10]
[9]
[8]
Bit
2.
fields in this register are modified only by the Host Controller Driver, except
HostControllerFunctionalState and RemoteWakeupConnected.
The HcControl register defines the operating modes for the Host Controller. Most of the
HcControl Register
Mnemonic
－
RWE
RWC
IR
31
15
30
14
Reserved
Reserved
RemoteWakeup
Enable
RemoteWakeup
Connected
Interrupt
Routing
29
13
Field name
28
12
27
11
TMPA901CM- 778
RWE
26
10
R
0
This bit is used by HCD to enable or disable the remote wakeup
feature upon the detection of upstream resume signaling. When this
bit is set and the ResumeDetected bit in HcInterruptStatus is set, a
remote wakeup is signaled to the host system. Setting this bit has no
impact on the generation of hardware interrupt.
This bit indicates whether the HC supports remote wakeup signaling. If
remote wakeup is supported and used by the system, it is the
responsibility of system firmware to set this bit during (Power on Self
Test) POST. The HC clears the bit upon a hardware reset but does not
alter it upon a software reset.
This bit determines the routing of interrupts generated by events
registered in HcInterruptStatus. If cleared, all interrupts are routed to
the normal host bus interrupt mechanism. If set, interrupts are routed
to the System Management Interrupt. HCD clears this bit upon a
hardware reset, but it does not alter this bit upon a software reset.
HCD uses this bit as a tag to indicate the ownership of the HC.
RWC
R/W
25
9
0
Reserved
24
IR
R
8
0
23
7
0
HCFS
R/W
22
6
0
Function
Address
R/W
BLE
21
5
R
0
CLE
20
4
R
0
(0xF450_0000) + (0x0004)
19
IE
3
R
0
PLE
TMPA901CM
18
2
R
0
2010-07-29
17
1
0
CBSR
R
16
0
0