TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 485

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(2) Aborting of Master Read transfers
You can abort Master Read transfers with the following operation:
1. Use UDC2 Command register to set the status of the relevant endpoint to
2. In order to stop the Master Read transfer, set 1 (Abort) to UDMSTSET
3. In order to confirm that the transfer is aborted, check that the mr_enable bit of
4. In order to initialize the Master Read transfer block, set 1 (Reset) to
5. Use the Command register (EP_FIFO_Clear) to initialize the FIFO for the
6. Use the Command register (EP_Enable) to enable the relevant endpoint.
Disabled (EP_Disable). (If aborted without making the endpoint disabled,
unintended data may be sent to the USB host.)
<mr_abort>.
DMAC Setting register was disabled to 0. Subsequent operations should not be
made while the mr_enable bit is 1.
(Information on the address where the transfer ended when aborted can be
confirmed with Master Read Current Address and Master Read AHB Address
registers.)
UDMSTSET<mr_reset>.
relevant endpoint.
TMPA901CM- 484
TMPA901CM
2010-07-29