TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 543

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

1.
2.
3.
EP0_MaxPacketSize register is set to “EP0_DATASET flag”.
can be cleared by writing 1 into the bit 0 (i_setup) of INT register. In case flags are
combined externally, read the INT register to confirm which flag is asserted and write
“1” into the relevant bit.
and wLength registers) to determine the request.
SETUP-Stage has finished. Since UDC2 does not allow writing data into the
Endpoint0-FIFO before this command is issued, it will keep returning "NAK" to the
IN-Token from the host until the command is issued.
byte size of the data to send is larger than the MaxPacketSize, divide them into groups
of MaxPacketSize before writing. When the number of data reached the
MaxPacketSize, the EP0_DATASET flag is asserted.
UDC2 deasserts the EP0_DATASET flag and asserts INT_EP0. Any data remaining to
be transmitted should be written into the Endpoint0-FIFO.
“EP_EOP” command to EP0 to inform UDC2 that it is a short packet. With this
command, UDC2 recognizes the end of the packet and transmits the short packet data.
finished.
Handshake for the STATUS-Stage. When the STATUS-Stage finished with no problem,
the INT_STATUS flag is asserted. When received a packet of STATUS-Stage from the
host before the “Setup_Fin” command is issued, UDC2 will return “NAK” and asserts
the INT_STATUS_NAK flag. Therefore, if this flag is asserted, be sure to issue the
“Setup_Fin” command.
SETUP-Stage
DATA-Stage
STATUS-Stage
The following description is based on the assumption that the bit 12 (dset) of
Then read Setup-Data storage registers (bRequest-bmRequestType, wValue, wIndex,
Finally, issue the “Setup_Received” command to inform UDC2 that the
Write the data to be transmitted to the IN-Token into the Endpoint0-FIFO. If the
When the data have been transmitted to the IN-Token from the host with no problem,
If the size of the data to be written is smaller than the MaxPacketSize, issue the
Finally, issue the “Setup_Fin” command to inform UDC2 that the DATA-Stage has
When the “Setup_Fin” command is issued, UDC2 will automatically make
UDC2 asserts the INT_SETUP flag when it has received the Setup-Token. This flag
TMPA901CM- 542
TMPA901CM
2010-07-29