TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 167

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

SELMEMC
3.10.1
circuit and DMC (Dynamic Memory Controller) circuit.
SMC and DMC function as independent circuits in memory controller. DMC and SMC circuits are
controlled by EBI (External Bus Interface).
Memory controllers (MPMC0 and MPMC1) have a built-in SMC (Static Memory Controller)
The external bus of SMC is used also as the external bus of DMC in the TMPA901CM. However,
Internal RAM2
Internal RAM0
EBI (External Bus Interface)
8KB(Remap)
Multi Layer Bus Matrix0
16KB
LCD Data Process
Peripheral Circuit
(Bus Master3)
(Bus Master4)
USB host 1.1 Controller
Accelerator
Controller
Data Cache
Other
LCD
16Kbyte
TimeOut Counter
Internal RAM1
Boot ROM
16KB
CPU Inst.
CPU Data.
8KB
DMA1
DMA2
LCDDA
LCDC
External Bus Interface
TMPA901CM-166
USB
LCDDA
CPU Inst.
LCDC
CPU Data
DMA1
DMA2
ARM926EJ-S
(Bus Master1&2)
Bus Interface
Bus swicther
EBI
CPU Data.
DMA1
DMA2
SMC
SDRAM
Memory
USB
MPMC0
Bus Matrix2
Multi Layer
Instruction Cache
DMC
(Bus Master5&6)
16Kbyte
(Bus Master7)
USB Device
Controller
Controller
DMA
SMC
MPMC1
Memory
NORF
Bus Matrix2
Multi Layer
TMPA901CM
2010-07-29
DMC