DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 93
![MCU 3V 16K 32-QFN](/photos/12/38/123805/32-qfn_pkg_sml.jpg)
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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3.8.2
When PFCR and PMRB are rewritten to switch the functions of external interrupt pins and when
the value of the ECPWME bit in AEGSR is rewritten to switch between selection and non-
selection of IRQAEC, the following points should be observed.
When a pin function is switched by rewriting PFCR or PMRB that controls an external interrupt
pin (IRQAEC, IRQ1, or IRQ0), the interrupt request flag is set to 1 at the time the pin function is
switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to
0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets
selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even
if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC).
Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function.
Figure 3.7 shows the procedure for setting a bit in PFCR and PMRB and clearing the interrupt
request flag. This procedure also applies to AEGSR setting.
When switching a pin function, mask the interrupt before setting the bit in PFCR and PMRB (or
AEGSR). After accessing PFCR and PMRB (or AEGSR), execute at least one instruction (e.g.,
NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is
executed immediately after PFCR and PMRB (or AEGSR) access without executing an
instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level. However, the procedure in figure 3.7 is
recommended because IECPWM is an internal signal and determining its value is complicated.
Notes on Switching Functions of External Interrupt Pins
Set PFCR and PMRB (or AEGSR) bit
Clear interrupt request flag to 0
Execute NOP instruction
I bit in CCR
I bit in CCR
Figure 3.7 PFCR and PMRB (or AEGSR) Setting
and Interrupt Request Flag Clearing Procedure
←
←
1
0
Interrupts masked. (Another possibility
is to disable the relevant interrupt in the
interrupt enable register 1.)
After setting PFCR and PMRB
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Interrupt mask cleared
Rev. 3.00 May 15, 2007 Page 59 of 516
Section 3 Exception Handling
REJ09B0152-0300
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