DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 532

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Rev. 3.00 May 15, 2007 Page 498 of 516
REJ09B0152-0300
Item
5.2.2 Standby Mode
5.2.3 Watch Mode
5.2.4 Subsleep Mode
5.2.5 Subactive Mode
Page Revisions (See Manual for Details)
88
88
89
89
Modified
… However, as long as the rated voltage is supplied,
the contents of CPU registers, on-chip RAM, and some
on-chip peripheral module registers are retained. …
Modified
… or the requested interrupt is disabled by the interrupt
enable bit.
When a reset source is generated in standby mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes and the t
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in watch mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in subsleep mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
Modified
… on the combination of bits SSBY, LSON, and TMA3
in SYSCR1 and bits MSON and DTON in SYSCR2.
Subactive mode is not cleared if the I bit in CCR is set
to 1 or the requested interrupt is disabled by the
interrupt enable register.
When a reset source is generated in subactive mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes and the t
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
REL
period has
REL
period has