DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 382
![MCU 3V 16K 32-QFN](/photos/12/38/123805/32-qfn_pkg_sml.jpg)
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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Section 16 I
16.7.4
In multimaster operation, if the master transmit is set with bit manipulation instructions in the
order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the
master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing. To
avoid this phenomenon, the following actions should be performed:
• In multimaster operation, use the MOV instruction to set bits MST and TRS.
• When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other
16.7.5
In master receive mode, SCL is fixed low on the falling edge of the 8th clock while the RDRF bit
is set to 1. When ICDRR is read around the falling edge of the 8th clock, the clock is only fixed
low in the 8th clock of the next round of data reception. The SCL is then released from its fixed
state without reading ICDRR and the 9th clock is output. As a result, some receive data is lost.
To avoid this phenomenon, the following actions should be performed:
• Read ICDRR in master receive mode before the rising edge of the 8th clock.
• Set RCVD to 1 in master receive mode and perform communication in units of one byte.
Rev. 3.00 May 15, 2007 Page 348 of 516
REJ09B0152-0300
than MST = 0 and TRS = 0, set MST = 0 and TRS = 0 again.
2
C Bus Interface 2 (IIC2)
Restriction on the Use of Bit Manipulation Instructions for MST and TRS
Setting in Multimaster Operation
Usage Note on Master Receive Mode
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