DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 345

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

The I
interface functions. The configuration of the registers that control the I
the Philips configuration, however. Figure 16.1 shows a block diagram of the I
Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1
• Selection of I
• Continuous transmission/reception
• Use of module standby mode enables this module to be placed in standby mode independently
I
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
Clock synchronous format
• Four interrupt sources
2
C bus format
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
when not used. (The IIC2 is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the
port/serial function is selected) and NMOS outputs when the bus drive function is selected.
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
2
C bus interface 2 conforms to and provides a subset of the Philips I
Features
2
C format or clock synchronous serial format
Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 3.00 May 15, 2007 Page 311 of 516
Section 16 I
2
C bus differs partly from
2
C bus (inter-IC bus)
2
C Bus Interface 2 (IIC2)
2
C bus interface 2.
REJ09B0152-0300