DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 41

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward compatible with
the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space.
• Upward-compatible with H8/300 CPUs
• General-register architecture
• Sixty-two basic instructions
• Eight addressing modes
• 64-Kbyte address space
• High-speed operation
CPU30H2C_000120030300
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers,
or eight 32-bit registers
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 2 states
8 × 8-bit register-register multiply:
16 ÷ 8-bit register-register divide:
16 × 16-bit register-register multiply:
32 ÷ 16-bit register-register divide:
Section 2 CPU
14 states
14 states
22 states
22 states
Rev. 3.00 May 15, 2007 Page 7 of 516
REJ09B0152-0300
Section 2 CPU