DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 256

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
Section 13 Asynchronous Event Counter (AEC)
13.3.6
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH
also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination
with ECL.
13.3.7
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL
also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination
with ECH.
Rev. 3.00 May 15, 2007 Page 222 of 516
REJ09B0152-0300
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Event Counter H (ECH)
Event Counter L (ECL)
Bit Name
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Bit Name
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Description
Either the external asynchronous event AEVH pin, φ/2,
φ/4, or φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source.
ECH can be cleared to H'00 when the CRCH bit in
ECCSR is cleared to 0.
Description
Either the external asynchronous event AEVL pin, φ/2,
φ/4, or φ/8 can be selected as the input clock source.
ECL can be cleared to H'00 when the CRCL bit in
ECCSR is cleared to 0.

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