DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 304

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.5
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev. 3.00 May 15, 2007 Page 270 of 516
REJ09B0152-0300
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Simultaneous Serial Data Transmission and Reception
Yes
No
No
Clear TE and RE bits in SCR to 0
Start transmission/reception
Data transmission/reception
Write transmit data to TDR
Set SPC3 bit in SPCR to 1
Read receive data in RDR
Read RDRF flag in SSR
Read TDRE flag in SSR
Read OER flag in SSR
continued?
TDRE = 1
RDRF = 1
OER = 1
<End>
Yes
Yes
No
No
(Clock Synchronous Mode)
Overrun error processing
Yes
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
For overrun error processing, see
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR.
TDRE flag is automatically cleared to
0.
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
RDRF flag is automatically cleared to
0.
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
If an overrun error occurs, read the
OER flag in SSR, and after performing
the appropriate error processing, clear
the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
figure 14.13.
When data is written to TDR, the
When data is read from RDR, the
When data is written to TDR, the