DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 336

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission and Reception: Data transmission and reception is a combined
operation of data transmission and reception which are described before. Transmission and
reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set
to 1 while the TDRE bit is set to 1, transmission and reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
Figure 15.9 shows a sample flowchart for serial transmit and receive operations.
Rev. 3.00 May 15, 2007 Page 302 of 516
REJ09B0152-0300
[1]
[2]
[3]
[4]
No
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations
Read TDRE in SSSR
Read RDRF in SSSR
Clear TEND to 0 and
Write transmit data
clear TE and RE in
Read receive data
Data transmission
Initialization
RDRF = 1?
TDRE = 1?
SSER to 0
in SSTDR
in SSRDR
continued?
Start
End
No
Yes
Yes
Yes
No
[2] Confirm that the RDRF bit is 1. If the RDRF
[3] Determine whether data transmission is continued.
[4] To end transmit and receive mode, clear the
[1] After reading SSSR and confirming that
TEND bit to 0 and clear the TE and RE bits in
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
SSER to 0.
the TDRE bit is 1, write transmit data in
SSTDR. Then the TDRE bit is automatically
cleared to 0.