DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 146

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 6 ROM
6.4.2
When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasure is performed in block units. Select a single block to be erased through erase block
3. The time during which the E bit is set to 1 is the flash memory erasing time.
4. The watchdog timer (WDT) is set to prevent the flash memory overerasing due to program
5. For writing dummy data to a verifying address, write one byte of data H'FF to an address
6. If the read data is not erased successfully, set erasing mode again, and repeat the
6.4.3
All interrupts including the NMI interrupt are disabled while flash memory is being programmed
or erased or while the boot program is executed for the following three reasons.
1. An interrupt during programming/erasure may cause a violation of the programming or erasing
2. If interrupt exception handling starts before programming the vector address or during
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
Rev. 3.00 May 15, 2007 Page 112 of 516
REJ09B0152-0300
register 1 (EBR1). To erase multiple blocks, each block must be erased in turn.
crush, etc. An overflow cycle of approximately 19.8 ms is adequate.
whose lower two bits are B'00. Verifying data can be read in longwords from the address to
which a dummy data is written.
erasing/erasing-verifying sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is 100.
algorithm, with the result that normal operation cannot be assured.
programming/erasure, a correct vector cannot be fetched and the CPU malfunctions.
carried out.
Erasing/Erasing-Verifying
Interrupt Handling when Programming/Erasing Flash Memory