DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 339

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.8
Serial Data Transmission
Figure 15.11 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in
synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS
pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
The difference between this mode and clocked synchronous communication mode is as follows:
when the SSU is set as a master device, the SSO pin is in the Hi-Z state if the SCS pin is in the Hi-
Z state and when the SSU is set as a slave device, the SSI pin is in the Hi-Z state if the SCS pin is
in the high-input state. The sample flowchart for serial data transmission is the same as that in
clocked synchronous communication mode.
Rev. 3.00 May 15, 2007 Page 305 of 518
REJ09B0152-0300