DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 293

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

14.4.3
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
data has been written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is
generated. Continuous transmission is possible because the TXI3 interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
serial transmission of the next frame is started.
state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
Serial
data
TDRE
TEND
LSI
operation
User
processing
Data Transmission
TXI3 interrupt
request
generated
1
Start
bit
0
D0
D1
TDRE flag
cleared to 0
Data written
to TDR
(8-Bit Data, Parity, One Stop Bit)
Transmit
1 frame
data
D7
Parity
0/1
bit
TXI3 interrupt request
generated
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Stop
bit
1
Start
bit
0
D0
1 frame
D1
Rev. 3.00 May 15, 2007 Page 259 of 518
Transmit
data
D7
TEI3 interrupt request
generated
Parity
0/1
bit
Stop
bit
1
REJ09B0152-0300
Mark
state
1