DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 533

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Item
5.2.6 Active (Medium-Speed)
Mode
5.3 Direct Transition
5.3.1 Direct Transition from Active
(High-Speed) Mode to Active
(Medium-Speed) Mode
Page Revisions (See Manual for Details)
90
91
91
When the RES pin goes low, the CPU goes into the
reset state and active (medium-sleep) mode is cleared.
In active (medium-speed) mode, the on-chip peripheral
Modified
In active (medium-speed) mode, the clock set by the
MA1 and MA0 bits in SYSCR1 is used as the system
clock, and the CPU and on-chip peripheral modules
function.
Active (medium-speed) mode is cleared by the SLEEP
instruction. When active (medium-speed) mode is
cleared, a transition to standby mode is made
depending on the combination of bits SSBY, LSON,
and TMA3 in SYSCR1, a transition to watch mode is
made depending on the combination of bits SSBY and
TMA3 in SYSCR1, or a transition to sleep mode is
made depending on the combination of bits SSBY and
LSON in SYSCR1. Moreover, a transition to active
(high-speed) mode or subactive mode is made by a
direct transition. Active (medium-sleep) mode is not
entered if the I bit in CCR is set to 1 or the requested
interrupt is disabled in the interrupt enable register.
modules function at the clock set by the MA1 and MA0
bits in SYSCR1.
The description in this section is modified.
Added
When a SLEEP instruction is executed in active (high-
speed) mode while the SSBY and LSON bits in
SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are set to 1, a transition is made to
active (medium-speed) mode via sleep mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (1).
Example: When φosc/8 is selected as the CPU
operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tosc =
115tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 499 of 516
REJ09B0152-0300