DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 227

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
11.3.7
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than φ
operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter,
RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the
FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
generated by dividing the system clock by 32, 16, 8, or 4 is output in active or sleep mode. φ
output in active, sleep, subactive, subsleep, or watch mode.
Bit
7
6
5
4
3
2
1
0
Bit Name
RCS6
RCS5
SUB32K
RCS3
RCS2
RCS1
RCS0
Clock Source Select Register (RTCCSR)
Initial
Value
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0.
Clock Output Selection
Select a clock output from the TMOW pin when enabling
TMOW output in PMR1.
000: φ/4
010: φ/8
100: φ/16
110: φ/32
xx1: φ
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φ
1001 to 1111: Setting prohibited
W
W
/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
W
/4 is selected, the RTC is disabled and
Rev. 3.00 May 15, 2007 Page 193 of 518
Section 11 Realtime Clock (RTC)
REJ09B0152-0300
W
is

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