DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 143

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

6.4
A software method using the CPU is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Programming mode, programming-verifying mode, erasing mode,
and erasing-verifying mode. The programming control program in boot mode and the user
programming/erasing control program in user program mode use these operating modes in
combination to perform programming/erasure. Flash memory programming and erasing should be
performed in accordance with the descriptions in section 6.4.1, Programming/Programming-
Verifying and section 6.4.2, Erasing/Erasing-Verifying, respectively.
6.4.1
When writing data or programs to the flash memory, the programming/programming-verifying
flowchart shown in figure 6.3 should be followed. Performing programming operations according
to this flowchart will enable data or programs to be written to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be performed on an erased area. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in bytes from the reprogramming data area or
5. The time during which the P bit is set to 1 is the programming time. Table 6.6 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verifying address, write 1-byte of data H'FF to an address whose lower
data has already been programmed.
performed even if programming fewer than 128 bytes. In this case, the remaining area must be
filled with H'FF.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.4, and additional programming data
computation according to table 6.5.
additional-programming data area to the flash memory. The programming address and 128-
byte data are latched in the flash memory. The lower eight bits of the start address in the flash
memory destination area must be H'00 or H'80.
allowable programming times.
An overflow cycle of approximately 6.6 ms is allowed.
two bits are B'00. Verifying data can be read in words or in longwords from the address to
which a dummy write was performed.
Flash Memory Programming/Erasure
Programming/Programming-Verifying
Rev. 3.00 May 15, 2007 Page 109 of 518
REJ09B0152-0300
Section 6 ROM