DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 319

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
15.3
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS receive data register (SSRDR)
• SS transmit data register (SSTDR)
• SS shift register (SSTRSR)
15.3.1
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Bit
7
6
Bit Name
MSS
BIDE
Register Descriptions
SS Control Register H (SSCRH)
Initial
Value
0
0
R/W
R/W
R/W
Description
Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically
cleared.
0: Operates as a slave device
1: Operates as a master device
Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 15.4.3, Relationship between Data
Input/Output and Shift Register. When the SSUMS bit in
SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
1: Bidirectional mode. Communication is performed by
using only one pin.
two pins.
Section 15 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 May 15, 2007 Page 285 of 518
REJ09B0152-0300

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