DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 276

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Note:
Rev. 3.00 May 15, 2007 Page 242 of 516
REJ09B0152-0300
Bit
3
2
1
0
*
Bit Name
PER
TEND
MPBR
MPBT
Only 0 can be written to clear the flag.
Initial
Value
0
1
0
0
R/W
R/(W)* Parity Error
R
R
R/W
Description
[Setting condition]
[Clearing condition]
When bit RE in SCR is cleared to 0, bit PER is not
affected and retains its previous state.
Transmit End
[Setting conditions]
[Clearing conditions]
Reserved
This bit is always read as 0 and cannot be modified.
Reserved
The write value should always be 0.
When a parity error is generated during reception
When 0 is written to PER after reading PER = 1
Receive data in which a parity error has occurred is
still transferred to RDR, but bit RDRF is not set.
Reception cannot be continued with bit PER set to
1. In clock synchronous mode, neither transmission
nor reception is possible when bit PER is set to 1.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
When 0 is written to TDRE after reading TDRE = 1
When the transmit data is written to TDR

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