DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 272

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Rev. 3.00 May 15, 2007 Page 238 of 516
REJ09B0152-0300
Bit
5
4
3
2
Bit Name
TE
RE
MPIE
TEIE
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, Bit
TDRE in SSR is cleared to 0 and serial data
transmission is started. Be sure to carry out SMR
settings, and setting of bit SPC3 in SPCR, to decide the
transmission format before setting bit TE to 1.
Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clock synchronous mode. Be sure to carry
out the SMR settings to decide the reception format
before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state
Reserved
Transmit End Interrupt Enable
When this bit is set to 1, the TEI3 interrupt request is
enabled. TEI3 can be released by clearing bit TDRE to
0 and clearing bit TEND to 0 in SSR, or by clearing bit
TEIE to 0.