DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 263

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

13.6
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within
Table 13.4 Maximum Clock Frequency
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR
5. The event counter PWM data register and event counter PWM compare register must be set so
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed)
f
f
Watch, subactive, subsleep, standby
φ
OSC
OSC
W
= 32.768 kHz or 38.4 kHz
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high
and low widths of the clock, see section 21, Electrical Characteristics. The duty cycle is
arbitrary.
second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
and ECPWDR should not be modified.
When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM)
before modifying these registers.
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
= 4 MHz to 10 MHz (2.7 to 3.6 V)
= 2 MHz to 4.2 MHz (1.8 to 3.6 V)
Usage Notes
Section 13 Asynchronous Event Counter (AEC)
(φ
(φ
(φ
(φ
(φ
(φ
(φ
(φ
OSC
OSC
OSC
W
W
W
W
OSC
)
/2)
/4)
/8)
/16)
/32)
/64)
Rev. 3.00 May 15, 2007 Page 229 of 516
/8)
Maximum Clock Frequency
Input to AEVH/AEVL Pin
2 to 4.2 MHz (1.8 to 3.6 V)
2 · f
f
1/2 · f
1/4 · f
2000 kHz
1000 kHz
500 kHz
250 kHz
4 to 10 MHz (2.7 to 3.6 V)
OSC
OSC
OSC
OSC
REJ09B0152-0300