DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 538

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Rev. 3.00 May 15, 2007 Page 504 of 516
REJ09B0152-0300
Item
Section 12 Watchdog Timer
12.2.1 Timer Control/Status
Register WD1 (TCSRWD1)
12.3.1 Watchdog Timer Mode
Figure 12.2 Example of Watchdog
Timer Operation
Figure 12.3 Interval Timer Mode
Operation
12.5.3 Clearing the WT/IT or
IEOVF Bit in TCSRWD2 to 0
Table 12.1 Assembly Program for
Clearing WT/IT or IEOVF Bit to 0
Page Revisions (See Manual for Details)
203
208
208
209
210
211
Added
Modified
… When a clock pulse is input after the TCWD count
value has reached H'FF, the watchdog timer overflows
and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles by
the on-chip oscillator (R
Modified
Modified
Added
Added
Internal reset
signal
count value
Bit Bit Name Description
0
TCWD
count value
H'FF
H'00
TCWD
H'FF
H'00
WRST
WT/IT = 1
H'F1
H'F1 written
to TCWD
request generated
Interval timer
Watchdog Timer Reset
Indicates whether a reset caused by the watchdog
timer is generated. This bit is not cleared by a reset
caused by the watchdog timer.
[Setting condition]
When TCWD overflows and an internal reset signal
is generated
interrupt
Start
request generated
H'F1 written to TCWD
Interval timer
interrupt
OSC
).
request generated
Interval timer
interrupt
512 clock cycles by R
request generated
Interval timer
Reset generated
interrupt
TCWD overflow
request generated
Interval timer
osc
interrupt
Time