DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 60

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 2 CPU
2.4.2
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
• Register Field
• Effective Address Extension
• Condition Field
Rev. 3.00 May 15, 2007 Page 26 of 516
REJ09B0152-0300
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
op
op
op
Figure 2.7 Instruction Formats
cc
EA(disp)
op
r n
r n
EA(disp)
r m
r m
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8