DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 302

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.4
Figure 14.12 shows an example of SCI3 operation for reception in clock synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart
for serial data reception.
Rev. 3.00 May 15, 2007 Page 268 of 516
REJ09B0152-0300
Serial
clock
Serial
data
RDRF
OER
LSI
operation
User
processing
output, starts receiving data.
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI3 interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated.
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode
RXI3
interrupt
request
generated
Serial Data Reception (Clock Synchronous Mode)
Bit 7
Bit 0
RDR data read
RDRF flag
cleared
to 0
1 frame
Bit 7
RXI3 interrupt
request generated
Bit 0
Bit 1
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
ERI3 interrupt request
generated by
overrun error
Overrun error
processing
Bit 7