DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 271

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

14.3.6
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer
clock source. For details on interrupt requests, refer to section 14.7, Interrupt Requests.
SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit
1
0
Bit
7
6
Bit Name
CKS1
CKS0
Bit Name
TIE
RIE
Serial Control Register (SCR)
Initial
Value
0
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 0 and 1
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 01 in subactive mode or
subsleep mode, the SCI3 can be used only when φ
selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 14.3.8, Bit Rate Register (BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI3 interrupt request is
enabled. TXI3 can be released by clearing the TDRE it
or TI bit to 0.
Receive Interrupt Enable
When this bit is set to 1, the RXI3 and ERI3 interrupt
requests are enabled.
RXI3 and ERI3 can be released by clearing the RDRF
bit or the FER, PER, or OER error flag to 0, or by
clearing the RIE bit to 0.
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
W
clock (n = 0)
Rev. 3.00 May 15, 2007 Page 237 of 518
REJ09B0152-0300
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is