DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 242

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 12 Watchdog Timer
12.3
12.3.1
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear
the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is
written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in
TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write
accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has
reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles by the on-chip oscillator (R
writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 12.2 shows an example of watchdog timer operation.
Rev. 3.00 May 15, 2007 Page 208 of 516
REJ09B0152-0300
Example:
Watchdog Timer Mode
Operation
Internal reset
signal
count value
TCWD
With 30-ms overflow period when φ = 4 MHz
Therefore, 256 – 15 = 241 (H'F1) is set in TCWD.
H'FF
H'00
4 × 10
8192
Figure 12.2 Example of Watchdog Timer Operation
H'F1
6
H'F1 written
to TCWD
× 30 × 10
–3
Start
= 14.6
H'F1 written to TCWD
512 clock cycles by R
Reset generated
TCWD overflow
OSC
osc
). TCWD is a