DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 299
![MCU 3V 16K 32-QFN](/photos/12/38/123805/32-qfn_pkg_sml.jpg)
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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14.5
Figure 14.9 shows the general format for clock synchronous communication. In clock
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clock
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clock synchronous mode, no parity bit is added. Inside the SCI3, the transmitter and
receiver are independent units, enabling full-duplex communication through the use of a common
clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be
read or written during transmission or reception, enabling continuous data transfer.
14.5.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal clock, the
serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of one
character, and when no transfer is performed the clock is fixed high.
14.5.2
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
Operation in Clock Synchronous Mode
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Clock
SCI3 Initialization
Figure 14.9 Data Format in Clock Synchronous Communication
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 3
8-bit
Bit 4
Rev. 3.00 May 15, 2007 Page 265 of 518
Bit 5
Bit 6
MSB
Bit 7
Don’t care
REJ09B0152-0300
*
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