DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 148

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 6 ROM
6.5
There are three types of flash memory programming/erasing protection; hardware protection,
software protection, and error protection.
6.5.1
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to the reset state, subactive mode, subsleep mode,
watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control
register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. For a reset by the RES
pin, the reset state is entered when the RES signal is held low until oscillation stabilizes after
switching on. For a reset during operation, hold the RES signal low for the RES pulse width
specified in the AC Characteristics section.
6.5.2
Software protection can protect programming/erasing of all flash memory blocks by clearing the
SWE bit in FLMCR1. When software protection is enabled, setting the P or E bit in FLMCR1
does not cause a transition to programming mode or erasing mode. By setting the erase block
register 1 (EBR1), erasing protection can be set for individual blocks. When EBR1 is set to H'00,
erasing protection is set for all blocks.
6.5.3
Error protection is a state in which programming/erasure is forcibly aborted when an error is
detected because CPU crush occurs during flash memory programming/erasure, or operation is not
performed in accordance with the programming/erasing algorithm. Aborting programming/erasure
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory address being programmed or erased is read (including vector read
• Exception handling excluding a reset is started during programming/erasure
• When the SLEEP instruction is executed during programming/erasure
Rev. 3.00 May 15, 2007 Page 114 of 516
REJ09B0152-0300
and instruction fetch)
Programming/Erasing Protection
Hardware Protection
Software Protection
Error Protection