DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 309

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

These interrupts are shown in table 14.14.
Table 14.14 Transmit/Receive Interrupts
Interrupt
RXI3
TXI3
TEI31
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Request Conditions
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, an
RXI3 is enabled and an interrupt is
requested. (See figure 14.17 (a).)
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, a TXI3 is
enabled and an interrupt is requested.
(See figure 14.17 (b).)
When the last bit of the character in TSR
is transmitted, if bit TDRE is set to 1, bit
TEND is set to 1. If bit TEIE is set to 1 at
this time, a TEI3 is enabled and an
interrupt is requested. (See figure 14.17
(c).)
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Notes
The RXI3 interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by repeating
the above operations until reception of the
next RSR data is completed.
The TXI3 interrupt routine writes the next
transmit data to TDR and clears bit TDRE
to 0. Continuous transmission can be
performed by repeating the above
operations until the data transferred to
TSR has been transmitted.
A TEI3 indicates that the next transmit
data has not been written to TDR when
the last bit of the transmit character in
TSR is transmitted.
Rev. 3.00 May 15, 2007 Page 275 of 518
REJ09B0152-0300