DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 312

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.4
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.18.
Thus, the reception margin in asynchronous mode is given by formula (1) below.
Where N: Ratio of bit rate to clock (N = 16)
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Rev. 3.00 May 15, 2007 Page 278 of 516
REJ09B0152-0300
M = (0.5 –
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Internal basic
clock
Receive data
(RXD3)
Synchronization
sampling timing
Data sampling
timing
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode



2N
1
) –
0
D – 0.5
8 clocks
Start bit
N
16 clocks
– (L – 0.5) F × 100(%)
7



15 0
D0
7
... Formula (1)
15 0
D1