DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 114

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 5 Power-Down Modes
5.1.2
SYSCR2 controls the power-down modes, as well as SYSCR1.
Rev. 3.00 May 15, 2007 Page 80 of 516
REJ09B0152-0300
Bit
7 to 5
4
3
2
1
0
System Control Register 2 (SYSCR2)
Bit Name

SA1
SA0
NESEL
DTON
MSON
Initial
Value
All 1
1
0
0
0
0
R/W

R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ
generates the oscillator clock (φ
sampling frequency of φ
system clock is used, clear this bit to 0.When the on-
chip oscillator is selected, set this bit to 1.
0: Sampling rate is φ
1: Sampling rate is φ
Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY,
TMA3, and LSON in SYSCR1 and bit MSON in
SYSCR2. For details, see table 5.2.
Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
Subactive Mode Clock Select 1 and 0
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
00: φ
01: φ
10: φ
11: φ
W
W
W
W
/8
/4
/2
W
) and the system clock pulse generator
OSC
OSC
/16.
/4.
OSC
when φ
OSC
). This bit selects the
W
is sampled. When a