DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 360

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
Section 16 I
Note:
16.3.6
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I
received after a start condition, the chip operates as the slave device.
16.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF. The initial value of ICDRT is H'FF.
Rev. 3.00 May 15, 2007 Page 326 of 516
REJ09B0152-0300
Bit
0
Bit
7 to 1
0
*
Bit Name
ADZ
Bit Name
SVA6 to
SVA0
FS
2
C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
Only 0 can be written to clear the flag.
2
C Bus Interface 2 (IIC2)
Slave Address Register (SAR)
I
2
C Bus Transmit Data Register (ICDRT)
Initial
Value
0
Initial
Value
All 0
0
R/W
R/(W)* General Call Address Recognition Flag
R/W
R/W
R/W
Description
This bit is valid in I
[Setting condition]
[Clearing condition]
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
Format Select
0: I
1: Clock synchronous serial format is selected.
2
When the general call address is detected in slave
receive mode
When 0 is written in ADZ after reading ADZ = 1
C bus format is selected.
2
2
C bus.
C bus format slave receive mode.

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