DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 381
![MCU 3V 16K 32-QFN](/photos/12/38/123805/32-qfn_pkg_sml.jpg)
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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16.7
16.7.1
The stop condition or start (re-transmit) condition should be issued after recognizing the falling
edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the
SCLO bit in the I2C control register 2 (ICCR2). Note that if the stop condition or start (re-
transmit) condition is issued in a particular timing and the situations shown below, these
conditions may not correctly output.
1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load
2. When the slave device elongates the low level period between the eighth and ninth clocks and
16.7.2
The WAIT bit in the I
set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during
the eighth clock, the high level period of the ninth clock may be shorter than a given period.
16.7.3
In multimaster operation, if the IIC transfer rate setting in this LSI is slower than those of the other
masters, SCL may be output with an unexpected width. To avoid this phenomenon, set the transfer
rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer
rate of the other masters is set to 400 kbps, the IIC transfer rate in this LSI should be set to 223
kbps (= 400/1.18) or more.
capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit.
activates the bit synchronous circuit.
Usage Notes
Note on Issuing Stop Condition and Start (Re-Transmit) Condition
Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)
Restriction on Transfer Rate Setting in Multimaster Operation
2
C bus mode register (ICMR) should be set to 0. Note that if the WAIT bit is
Rev. 3.00 May 15, 2007 Page 347 of 516
Section 16 I
2
C Bus Interface 2 (IIC2)
REJ09B0152-0300
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