MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 99

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
If a ColdFire processor encounters any type of fault during the exception processing of
another fault, the processor immediately halts execution with the catastrophic fault-on-fault
condition. A reset is required to force the processor to exit this halted state.
Exception
Exception
Exception
Interrupt
Reset
Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized
and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt
vector.
Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception
priority; it provides for system initialization and recovery from catastrophic failure. When assertion of
RSTI is recognized, current processing is aborted and cannot be recovered. The reset exception
places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T].
This exception also clears SR[M] and sets the processor’s interrupt priority mask in the SR to the
highest level (level 7). Next, the VBR is initialized to 0x0000_0000. Configuration registers controlling
the operation of all processor-local memories (cache and RAM modules on the MCF5272) are
invalidated, disabling the memories.
Note: Other implementation-specific supervisor registers are also affected. Refer to each of the
modules in this manual for details on these registers.
If the processor is not halted and it has ownership of the bus, it initiates the reset exception by
performing two longword read bus cycles. The longword at address 0 is loaded into the stack pointer
and the longword at address 4 is loaded into the PC. After the initial instruction is fetched from
memory, program execution begins at the address in the PC. If an access error or address error
occurs before the first instruction executes, the processor enters the fault-on-fault halted state.
Table 2-21. MCF5
Chapter 2. ColdFire Core
272
Exceptions (Continued)
Description
Exception Processing Overview
2-31