MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 265
![PROCESSOR MODULE FLASH MOD5272](/photos/6/75/67555/mod5272-100ir_sml.jpg)
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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- Download datasheet (6Mb)
MOTOROLA
12.2.1.4 Endpoint Controllers
The MCF5272 has eight independent endpoint controllers that manage data transfer
between the on-chip CPU and the USB host for each endpoint. These controllers provide
event notification to the user and manage the IN and OUT FIFO dual-port RAM buffers.
The USB endpoint configuration registers (USBEPOCFGn or USBEPICFGn) are used to
configure each endpoint to support either control, interrupt, bulk, or isochronous transfers.
USB always uses endpoint 0 as a control pipe, so it must be configured for control transfer
mode. Additional control pipes can be provided by other endpoints.
A total of 1024 bytes of dual-port RAM are available for transmit and receive FIFO buffers.
This RAM is partitioned to provide 512 bytes for each direction. The user is responsible for
configuring the FIFO for each endpoint. This configuration is flexible within the following
constraints:
For example, an endpoint with a maximum packet size of 32 bytes can have a FIFO size of
64, 128, or 256 bytes and a starting address of 0, 64, 128, 192, 256, etc.
12.2.1.5 USB Request Processor
The MCF5272 USB request processor automatically processes all of the USB standard
requests listed in Table 12-1 except for
request. The
• For received data:
• For error detection:
• FIFO size must be an integral power of 2
• FIFO size must be at least twice the maximum packet size
• FIFO starting address must be aligned on a boundary defined by the FIFO size.
— NRZI encoding
— Bit stuffing
— Sync detection
— Packet identification
— End-of-packet detection
— Serial-to-parallel conversion
— CRC validation
— NRZI decoding
— Bit unstuffing
— Bad CRC
— Timeout waiting for end-of-packet
— Bit stuffing violations
SYNC
_
FRAME
Chapter 12. Universal Serial Bus (USB)
request is passed to the user as a vendor-specific request. The
SYNC
_
FRAME
and the optional
SET
Module Operation
_
DESCRIPTOR
12-5
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