MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 278

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Register Description and Programming Model
12-18
Bits
5–4
3–2
10
9
8
7
6
CFG_RAM_VAL Enable USB configuration RAM. Notifies the USB module that the user has loaded the
CMD_OVER
CMD_ERR
CRC_ERR
OUT_LVL
IN_LVL
Name
—
Table 12-12. EP0CTL Field Descriptions (Continued)
configuration RAM. Must be set in order for the USB module to process the USB
standard device requests that access the configuration RAM. These requests are
GET
accesses to the configuration RAM cause an access error.
0 Configuration RAM invalid
1 Configuration RAM valid
Command error for device request interface. Used to indicate to the endpoint controller
that an error has been encountered during class or vendor specific device request or
SYNCH_FRAME command processing. This command bit is write only and always
returns 0 when read.
Result of Request
Processed device request successfully
Error processing the request
Busy processing the request
Note: CMD_OVER and CMD_ERR have to be written simultaneously. The CMD_OVER
and CMD_ERR bits control the status stage response for vendor and class specific
requests.
Command over for device request interface. Used to indicate to the endpoint controller
that processing of a class or vendor specific device request or SYNCH_FRAME
command has been completed by the user. This command bit is write only and always
returns 0 when read.
Note: CMD_OVER and CMD_ERR have to be written simultaneously. The CMD_OVER
and CMD_ERR bits control the status stage response for vendor and class specific
requests.
CRC error generation enable. This bit enables CRC error generation for debug and test
purpose. In order to use this feature, the DEBUG bit must be set. Enabling this bit causes
a CRC error on the next data packet transmitted. The CRC_ERR bit must be set again in
order to generate another CRC error. This bit only applies to IN transfers. This command
bit is write-only and always returns 0 when read.
1 CRC error generation if DEBUG = 1
0 default value
Reserved, should be cleared.
Endpoint 0 OUT FIFO level for interrupt. This field selects the FIFO level to generate an
OUT_LVL interrupt. The OUT_LVL interrupt is generated when the FIFO fills above the
selected level.
00 FIFO 25% Full
01 FIFO 50% Full
10 FIFO 75% Full
11 FIFO 100% Full
Endpoint 0 IN FIFO level for interrupt. This field selects the FIFO level to generate an
IN_LVL interrupt. The IN_LVL interrupt is generated when the FIFO falls below the
selected level.
00 FIFO 25% Empty
01 FIFO 50% Empty
10 FIFO 75% Empty
11 FIFO 100% Empty
_
DESCRIPTOR
,
MCF5272 User’s Manual
SET
_
CONFIGURATION
Description
, and
CMD_OVER
1
1
0
SET
_
INTERFACE
. When this bit is set,
CMD_ERR
0
1
X
MOTOROLA