MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 301

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
The maximum transmission rate for each GCI/IDL port is 144 Kbps: the sum of two
64-Kbps B channels and one 16-Kbps D-channel. Frames of B
packed together in a similar way to the receive side.
Because the reception and transmission of information on the GCI/IDL interface is
deterministic, a common interrupt is generated at the 2-KHz rate. It is expected that a
common interrupt service routine services the transmit and receive registers.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all
ones.
13.2.3 GCI/IDL B- and D-Channel Bit Alignment
Unencoded voice is normally presented on the physical line most significant bit first (left
aligned). See the MC145484 data sheet for an example. Accordingly, the MCF5272
normally assumes incoming data are left-aligned.
However, this convention is reversed when the data stream is HDLC (high-level data link
control) encoded. HDLC-stuffing and unstuffing are done by counting bits from the lsb. The
look-up table in the software HDLC on this device transmits the lsb first.
13.2.3.1 B-Channel Unencoded Data
Because unencoded voice data appears on the physical interface most significant bit (msb)
first, the msb is left aligned in the transmit and receive shift register; that is, the first bit of
B-channel received data is aligned in the msb position as shown in Figure 13-6.
The CPU uses longword (32-bit) registers (like P0B1RR) to communicate B-channel data
to/from the PLIC. These registers are loaded by concatenating four of the 8-bit/8-KHz
frames. The four frames are aligned sequentially as shown in Figure 13-6, with the first
Shadow Register
B1, B2 Transmit
Data Register
Figure 13-5. GCI/IDL B Data Transmit Register Multiplexing
START
Chapter 13. Physical Layer Interface Controller (PLIC)
8 bits
8 bits
Shift Register
32 bits
8 bits
MUX
32
32
8 bits
2-KHz transfer and interrupt
1
8-KHz Rate
Internal Bus
, B
8 bits
2
, and D-channels are
END
GCI/IDL Block
13-5