MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 19

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
19.15.4
19.15.5
19.15.6
19.15.7
19.16
19.16.1
19.16.1.1
19.16.1.2
19.16.1.3
19.16.1.4
19.16.1.5
19.16.1.6
19.16.1.7
19.16.1.8
19.16.1.9
19.16.2
19.16.2.1
19.16.2.2
19.16.2.3
19.16.2.4
19.16.2.5
19.16.2.6
19.16.3
19.16.3.1
19.16.3.2
19.16.3.3
19.16.3.4
19.17
19.17.1
19.17.2
19.17.3
19.17.4
19.17.5
19.17.6
19.17.7
19.17.8
19.17.9
19.17.10
19.18
19.19
Paragraph
Number
Physical Layer Interface Controller TDM Ports and UART 1 ....................... 19-31
JTAG Test Access Port and BDM Debug Port............................................... 19-36
Operating Mode Configuration Pins............................................................... 19-38
Power Supply Pins .......................................................................................... 19-39
Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0).................... 19-30
Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................ 19-31
Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............. 19-31
Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)............ 19-31
GCI/IDL TDM Port 0. ................................................................................ 19-31
GCI/IDL TDM Port 1 ................................................................................. 19-33
GCI/IDL TDM Ports 2 and 3...................................................................... 19-34
Test Clock (TCK/PSTCLK) ....................................................................... 19-36
Test Mode Select and Force Breakpoint (TMS/BKPT).............................. 19-36
Test and Debug Data Out (TDO/DSO)....................................................... 19-37
Test and Debug Data In (TDI/DSI) ............................................................ 19-37
JTAG TRST and BDM Data Clock (TRST/DSCLK) ................................ 19-37
Motorola Test Mode Select (MTMOD)...................................................... 19-37
Debug Transfer Error Acknowledge (TEA) ............................................... 19-37
Processor Status Outputs (PST[3:0]) .......................................................... 19-37
Debug Data (DDATA[3:0])........................................................................ 19-38
Device Test Enable (TEST)........................................................................ 19-38
Frame Sync (FSR0/FSC0/PA8).............................................................. 19-31
D-Channel Grant (DGNT0/PA9)............................................................ 19-32
Data Clock (DCL0/URT1_CLK) ........................................................... 19-32
Serial Data Input (DIN0/URT1_RxD).................................................... 19-32
UART1 CTS (URT1_CTS/QSPI_CS2) ................................................. 19-32
UART1 RTS (URT1_RTS/INT5)........................................................... 19-32
Serial Data Output (DOUT0/URT1_TxD) ............................................. 19-32
D-Channel Request(DREQ0/PA10) ....................................................... 19-33
QSPI Chip Select 1 (QSPI_CS1/PA11).................................................. 19-33
GCI/IDL Data Clock (DCL1/GDCL1_OUT)......................................... 19-33
GCI/IDL Data Out (DOUT1) ................................................................. 19-33
GCI/IDL Data In (DIN1) ........................................................................ 19-34
GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ......................................... 19-34
D-Channel Request (DREQ1/PA14) ...................................................... 19-34
D-Channel Grant (DGNT1_INT6/PA15_INT6) .................................... 19-34
GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .................................. 19-35
GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .................................. 19-35
QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7
INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ................................... 19-36
(PA7/DOUT3/QSPI_CS3).................................................................. 19-35
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