MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 174

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Programming Model
Table 6-6 details the interaction between the PDN and WK bits for the USB and USART
modules.
6.2.6 Activate Low-Power Register (ALPR)
ALPR, Figure 6-6, is used to put the MCF5272 into a low power mode (sleep or stop). A
low-power mode is activated by a write access with any data to ALPR followed by a STOP
instruction.
The sequence to enter sleep mode is as follows:
6-10
PDN WK
Bits
3-0
0
1
1
4
1. Set power down and wakeup enable bits in the PMR as desired; set PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the
X
0
1
level do not reactivate the CPU. Note that any interrupt will cause the processor to
exit low-power mode, but only unmasked interrupts will cause the processor to
resume operation.
write to the ALPR.
SLPEN
Field
Address
Module powered up and operating normally.
Module in power down and can only be reactivated by clearing PDN.
Module in power down and can be reactivated by clearing PDN or detecting signal on the receive pins.
—
Reset
Field
R/W
15
Sleep enable. Allows the MCF5272 to be put into sleep mode in which internal clocking to the
CPU is disabled.To enter sleep mode, the user must write to the ALPR and then execute a
STOP instruction. See Section 6.2.6, “Activate Low-Power Register (ALPR).” Individual
modules may have clocking disabled through the appropriate PDN bits. After SLPEN is set, a
write access must be made to ALPR to actually enter sleep mode. D[31:0] are driven low, and
other bus signals are negated. Sleep mode is exited when an interrupt is detected from an
on-chip peripheral or one of the external interrupt pins, INT[6:1].
0 Sleep mode disabled.
1 Sleep mode enabled.
Reserved, should be cleared.
Figure 6-6. Activate Low-Power Register (ALPR)
Table 6-6. USB and USART Power Down Modes
Table 6-5. PMR Field Descriptions (Continued)
MCF5272 User’s Manual
0000_0000_0000_0000
MBAR + 0x00E
Write only
Description
ALPHR
Description
0
MOTOROLA