MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 235

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
11.5 Programming Model
This section gives an overview of the registers, followed by a description of the buffers.
The FEC is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control and to extract global status information.
The descriptors are used to pass data buffers and related buffer information between the
hardware and software.
Table 11-6 shows the FEC register memory map with each register address, name, and a
brief description.
The following sections describe each register in detail.
0xC40 -
0x8CC
0xC0C
Offset
0x84C
0x8D0
0x8EC
0xC00
0xC04
0xC08
0xC10
0xC14
0xC18
0xDFF
0x8E4
0x840
0x844
0x848
0x850
0x854
0x880
0x884
0x944
0x948
0x984
ECR
EIR
EIMR
IVSR
RDAR
TDAR
MMFR
MSCR
FRBR
FRSR
TFSR
TFWR
RCR
MFLR
TCR
MALR
MAUR
HTUR
HTLR
ERDSR
ETDSR
EMRBR
EFIFO
Table 11-6. FEC Register Memory Map
Name
Chapter 11. Ethernet Module
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Ethernet control register, [p. 11-12]
Interrupt event register, [p. 11-13]
Interrupt mask register, [p. 11-14]
Interrupt vector status register, [p. 11-14]
Receive descriptor active register, [p. 11-15]
Transmit descriptor active register, [p. 11-16]
MII management frame register, [p. 11-17]
MII speed control register, [p. 11-18]
FIFO receive bound register, [p. 11-20]
FIFO receive start register, [p. 11-20]
FIFO transmit start register, [p. 11-22]
Transmit FIFO watermark, [p. 11-21]
Receive control register, [p. 11-23]
Maximum frame length register, [p. 11-24]
Transmit control register, [p. 11-25]
Lower 32-bits of MAC address
Upper 16-bits of MAC address
Upper 32-bits of hash table, [p. 11-27]
Lower 32-bits of hash table, [p. 11-27]
Pointer to receive descriptor ring, [p. 11-28]
Pointer to transmit descriptor ring, [p. 11-29]
Maximum receive buffer size, [p. 11-29]
FIFO RAM space
Description
Programming Model
11-11