MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 107

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
Chapter 4
Local Memory
This chapter describes the MCF5272 implementation of the ColdFire Version 2 core local
memory specification. It consists of the following sections.
4.1 Interactions between Local Memory Modules
Depending on configuration information, instruction fetches and data read accesses may be
sent simultaneously to the SRAM, ROM, and cache controllers. This approach is required
because the controllers are memory-mapped devices and the hit/miss determination is made
concurrently with the read data access. Power dissipation can be minimized by configuring
the ROM and SRAM base address registers (ROMBAR and RAMBAR) to mask unused
address spaces whenever possible.
If the access address is mapped into the region defined by the SRAM (and this region is not
masked), it provides the data back to the processor and any cache or ROM data is discarded.
If the access address does not hit the SRAM, but is mapped into the region defined by the
ROM (and this region is not masked), the ROM provides the data back to the processor and
any cache data is discarded. Accesses from the SRAM and ROM modules are never cached.
The complete definition of the processor’s local bus priority scheme for read references is
as follows:
if (SRAM “hits”)
• Section 4.3, “SRAM Overview,” and Section 4.4, “ROM Overview,” describe the
• Section 4.5, “Instruction Cache Overview,” describes the cache implementation,
on-chip static RAM (SRAM) and ROM implementations. These chapters cover
general operations, configuration, and initialization. They also provide information
and examples showing how to minimize power consumption when using the ROM
and SRAM.
including organization, configuration, and coherency. It describes cache operations
and how the cache interfaces with other memory structures.
SRAM supplies data to the processor
if (ROM “hits”)
ROM supplies data to the processor
else if (cache “hits”)
cache supplies data to the processor
Chapter 4. Local Memory
else system memory reference to access data
4-1