MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 114

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Instruction Cache Overview
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte
lines are loaded into the instruction cache.
The instruction cache also contains a 16-byte fill buffer that provides temporary storage for
the last line fetched in response to a cache miss. With each instruction fetch, the contents
of the line-fill buffer are examined. Thus, each instruction fetch address examines both the
tag memory array and the line-fill buffer to see if the desired address is mapped into either
hardware resource. A cache hit in either the memory array or the line-fill buffer is serviced
in a single cycle. Because the line-fill buffer maintains valid bits on a longword basis, hits
in the buffer can be serviced immediately without waiting for the entire line to be fetched.
If the referenced address is not contained in the memory array or the line-fill buffer, the
instruction cache initiates the required external fetch operation. In most situations, this is a
16-byte line-sized burst reference.
Hardware is nonblocking, meaning the ColdFire core's local bus is released after the initial
access of a miss. Thus, the cache, SRAM, or ROM module can service subsequent requests
while the rest of the line is being fetched and loaded into the fill buffer.
Generally, longword references are used for sequential fetches. If the processor branches to
an odd word address, a word-sized fetch is generated. The memory array of the instruction
cache is enabled only if CACR[CENB] is asserted.
4-8
31
Local Address Bus
9
Figure 4-3. Instruction Cache Block Diagram
43
1 2
0
Fill Hit
=
MCF5272 User’s Manual
31
Line
31
Tag Hit
Tag
=
Address
9
Buffer
0
31
4
Line Buffer Data Storage
External Data[31:0]
31
MUX
Local Data Bus
Data
MUX
0
0
63
MOTOROLA