MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 171

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
Table 6-4 describes SPR fields.
6.2.5 Power Management Register (PMR)
The power management register (PMR), Figure 6-5, is used to control the various
low-power options including low-power sleep, low-power stop, and powering down
individual on-chip modules.
15, 7
14, 6
13, 5
12, 4 PE, PEEN Peripheral error. This bit is set when an access to an on-chip peripheral is terminated with a
11, 3
10, 2
Bits
9, 1
8, 0
WPVEN
HWTEN
ADCEN
SMVEN
RPVEN
EXTEN
SUVEN
Fields
WPV,
HWT,
ADC,
SMV,
RPV,
SUV,
EXT,
Address decode conflict. This bit is set when an address matches against two chip selects. If
ADCEN is also set, the bus cycle is terminated with an access error exception.
Write protect violation. This bit is set when a write access is attempted to an area for which the
chip select is set to read only. If WPVEN is also set, the bus cycle is terminated with an access
error exception.
Stopped module violation. This bit is set when an access is attempted to an on-chip peripheral
whose clock has been stopped. If SMVEN is also set, the bus cycle is terminated with an access
error exception.
transfer error. If PEEN is also set, the bus cycle is terminated with an access error exception.
Hardware watchdog timeout. This bit is set when the hardware watchdog timer has reached its
programmed timeout value. If HWTEN is also set, the bus cycle is terminated with an access
error exception.
Read protect violation. This bit is set when a read access is attempted to an area for which the
chip select is set to write only. If RPVEN is also set, the bus cycle is terminated with an access
error exception.
External transfer error. This bit is set when an external transfer error is reported to the SIM on
TEA. If EXTEN is also set, the bus cycle is terminated with an access error exception.
Supervisor/user violation. This bit is set when a user mode access is attempted to an area for
which the chip select is set to supervisor only. If SUVEN is also set, the bus cycle is terminated
with an access error exception.
Chapter 6. System Integration Module (SIM)
Table 6-4. SPR Field Descriptions
Description
Programming Model
6-7