MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 306

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

GCI/IDL Block
13.2.5 GCI/IDL Interrupts
The PLIC module generates two interrupts—the periodic frame interrupt and the aperiodic
status interrupt.
13.2.5.1 GCI/IDL Periodic Frame Interrupt
The frame interrupt is a periodic 2-KHz interrupt as shown in Figure 13-10. This is the
normal interrupt rate for servicing the incoming and outgoing B and D channels. This
service routine must execute in a timely manner. Each of the B- and D-channel transmit and
receive registers should be written and read prior to the next 2-KHz interrupt for underrun
or overrun conditions to be prevented.
Note that only the active, that is enabled, B- and D-channel receive and transmit registers
need to be read and written. B and D channels which are not active need not have their
receive and transmit registers read and written.
It should be clear from Figure 13-10 that due to the double buffering through the PLIC
shadow register, frame (n) is written to the PLIC transmit register during the interrupt
service routine of the previous frame, frame (n-1). Similarly on the receive side, frame (n)
is read from the PLIC receive register during the interrupt service routine of the following
frame, frame (n + 2). Figure 13-10 shows that the minimum delay through the PLIC, when
not in loopback mode, is two 2-KHz frames, or 1 mS.
13.2.5.2 GCI Aperiodic Status Interrupt
The aperiodic status interrupt is an interrupt which is driven by a number of conditions. The
CPU services this interrupt by reading the aperiodic status register, ASR, and by reading or
writing the relevant C/I or monitor channel register or registers which have generated this
interrupt. Once read, the interrupt is cleared. Each port and individual interrupts within each
port is maskable. The following conditions for each of the ports can trigger this interrupt:
13-10
Slot 0
125 µ s
2-KHz interrupt
Read Frame n -1 (B&D)
Write Frame n + 1 (B&D)
Interrupt service routine
Slot 1
Frame n
500 µ s
Slot 2
Figure 13-10. Periodic Frame Interrupt
Slot 3
2-KHz interrupt
MCF5272 User’s Manual
Slot 0
Interrupt service routine
Read Frame n (B&D)
Write Frame n + 2 (B&D)
Slot 1
Frame n + 1
Slot 2
Slot 3
2-KHz interrupt
Slot 0
Interrupt service routine
Read Frame n + 1 (B&D)
Write Frame n + 3 (B&D)
Frame n + 2
Slot 1
MOTOROLA
Slot 2