MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 478

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Reset Operation
The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and
QSPI_CS0/BUSW0, are sampled when RSTI negates and select the port size of CS0 and
the physical data bus width after a master reset occurs. The INTx signals are synchronized
and are registered on the last falling edge of CLKIN where RSTI is asserted.
A master reset causes any bus cycle (including SDRAM refresh cycles) to terminate. In
addition, master reset initializes registers appropriately for a reset exception. During an
external master reset, SCR[RSTSRC] is set to 0b11 to indicate that assertion of RSTI and
DRESETEN caused the previous reset.
20.12.2 Normal Reset
External normal resets should be performed anytime it is important to maintain the data
stored in SDRAM during a reset. An external normal reset is performed when an external
device asserts RSTI while negating DRESETEN. At power on reset both RSTI and
DRESETEN must be asserted simultaneously. If DRESETEN is not asserted at the same
time as RSTI at power up the SDRAMC cannot be initialized by software.
During an external normal reset, RSTI must be asserted for a minimum of six CLKINs.
Figure 20-22 is a functional timing diagram of external normal reset operation, illustrating
relationships among RSTI, DRESETEN, RSTO, mode selects, and bus signals. RSTI and
DRESETEN are internally synchronized on consecutive falling and rising clocks before
being used and must meet the specified setup and hold times to the falling edge of CLKIN
only if recognition by a specific falling edge is required
The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1,
QSPI_CS0/BUSW0, and HiZ are sampled when RSTO negates and select the port size of
CS0 and the physical data bus width after a master reset occurs. RSTO is asserted as long
20-24
.
CLKIN
VDD
RSTI
DRESETEN
Mode Select
Inputs
RSTO
BUS SIGNALS
(H)
Figure 20-22. Normal Reset Timing
MCF5272 User’s Manual
CLK CYCLES
T >= 6
CLK CYCLES
T = 32,768
CLK CYCLES
T >= 22
MOTOROLA