MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 237

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
11.5.3 Interrupt Mask Register (EIMR)
The EIMR register provides control over which possible interrupt events are allowed to
actually cause an interrupt.This register is cleared upon a hardware reset.
Reset
Reset
Field HBERR BABR BABT GRA
Field
Addr
R/W
R/W
20–0
Bits
31
30
29
28
27
26
25
24
23
22
21
31
15
HBERR
EBERR
UMINT
Name
BABR
BABT
GRA
RXF
RXB
TXF
TXB
MII
—
30
Heartbeat error. A heartbeat was not detected within the heartbeat window following a
transmission.
Babbling receive error. A frame was received with length in excess of MAX_FL bytes.
Babbling transmit error. The transmitted frame length has exceeded MAX_FL bytes. This
condition is usually caused by a frame that is too long being placed into the transmit data
buffer(s). Truncation does not occur.
Graceful stop complete. A graceful stop, which was initiated by setting X_CTRL[GTS], is now
complete. This bit is set as soon as the transmitter has finished transmitting any frame that
was in progress when GTS was set.
Transmit frame interrupt. A frame has been transmitted and that the last corresponding buffer
descriptor has been updated.
Transmit buffer interrupt. A transmit buffer descriptor has been updated.
Receive frame interrupt. A frame has been received and the last corresponding buffer
descriptor has been updated.
Receive buffer interrupt. A receive buffer descriptor has been updated.
MII interrupt. The MII has completed the data transfer requested.
FEC bus error. A bus error occurred when the FEC was accessing an internal bus.
Unmasked interrupt status. An interrupt is currently being asserted to the interrupt controller.
This bit is not maskable.
Reserved, should be cleared.
29
Table 11-8. EIR Field Descriptions
28
TXF
Chapter 11. Ethernet Module
27
TXB
26
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x844
RXF
Read/write
Read/write
25
—
Description
RXB
24
MII EBERR UMINT
23
22
21
Programming Model
20
—
11-13
16
0