MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 192

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Chip Select Registers
Table 8-3 describes the interaction between CSBRn[EBI], OE/RD, R/W, and SDWE.
8-4
Bits
4–2
1
0
Table 8-3. Output Read/Write Strobe Levels versus Chip Select EBI Code
ENABLE Enable. Disables/enables the chip select. When disabled, the chip select is never asserted,
Name
CTM
TM
EBI
00
01
11
The MCF5272 compares the address for the current bus
transfer with the address and mask bits in the CSBRs and
CSORs looking for a match. The priority is listed in Table 8-4
(from highest priority to lowest priority):
Transfer modifier. Operates with TT to determine the access type.
TT
0x
0x
0x
0x
0x
0x
0x
10
10
10
10
11
11
11
11
11
11
11
11
Compare TM. Enables comparison between the access type and the TM and TT bits.
0 TT and TM register bits do not affect address match.
1 TT and TM register bits must match the access type for an address match to occur.
regardless of the address on the internal bus. ENABLE is 0 at reset, except CS0 which is 1.
0 Chip select is disabled, no matches can occur and chip select output cannot assert.
1 Chip select is enabled, bus cycles are compared against register contents.
Table 8-2. CSBRn Field Descriptions (Continued)
EBI Function
SRAM, ROM
SRAM, ROM
TM
000
001
010
011–100
101
110
111
000–100
101
110
111
000
001
010
011
100
101
110
111
SDRAM
Function
Reserved
User data access
User instruction access
Reserved
Supervisor data access
Supervisor instruction access
Reserved
Reserved
Emulator mode data access
Emulator mode instruction access
Reserved
CPU space access
Interrupt acknowledge level 1
Interrupt acknowledge level 2
Interrupt acknowledge level 3
Interrupt acknowledge level 4
Interrupt acknowledge level 5
Interrupt acknowledge level 6
Interrupt acknowledge level 7
MCF5272 User’s Manual
Access Type
Write
Read
Write
Read
Write
Read
NOTE:
Description
OE/RD
High
High
High
High
Low
Low
R/W
High
High
High
High
Low
Low
SDWE
High
High
High
High
High
Low
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