MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 411

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
18.3.1 PWM Control Register (PWCRn)
This register, shown in Figure 18-2, controls the overall operation of the PWM. Unless
disabled and then re-enabled, writing to PWCR while the PWM is running will not alter its
operation until the current output cycle finishes. For example, if the prescale value is
changed while the PWM is enabled, the new value will not take effect until after the counter
has “wrapped around”. The PWM must be disabled and then re-enabled to affect its
operation before the end of the current output cycle.
Table 18-2 gives PWCR field descriptions.
Bits
3–0
7
6
5
4
Name
FRC1 Force output high.
CKSL Prescale clock. These bits select the clock frequency divider, that is, the output of the
LVL
EN
—
Address
Reset
Field
R/W
Enable.
0 Disables the PWM. While disabled, the PWM is in low-power mode and the prescaler
1 Enables the PWM.
0 Default reset value. PWM functions normally.
1 The PWM drives the output high for the entire counter period. PWCRn[FRC1] has a
Disable level. Determines the PWM output level whenever the PWM is disabled.
0 The PWM output is low while disabled.
1 The PWM output is high while disabled.
Reserved, should be cleared.
divider chain, as shown below.
CKSL[3:0] Divisor
does not count. When the PWM is disabled, the output is forced to the value of
PWCRn[LVL].
lower priority than PWCRn[EN], so setting PWCRn[FRC1] while PWCRn[EN] is
cleared has no effect. There are two ways to drive the PWM output high. If PWCRn[EN]
is cleared, PWM output immediately assumes the value of PWCRn[LVL]. If
PWCRn[FRC1] is set while PWCRn[EN] is set, the PWM output does not go high until
after the current output cycle completes.
0000
0001
0010
...
1111
Figure 18-2. PWM Control Registers (PWCRn)
Chapter 18. Pulse Width Modulation (PWM) Module
EN
7
MBAR + 0x0C0 (PWCR0); + 0x0C4 (PWCR1); + 0x0C8 (PWCR2)
Table 18-2. PWCRn Field Descriptions
32768
...
1
2
4
FRC1
6
LVL
5
—
4
0010_0000
Read/Write
Description
3
CKSEL
PWM Programming Model
0
18-3