MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 225
![PROCESSOR MODULE FLASH MOD5272](/photos/6/75/67555/mod5272-100ir_sml.jpg)
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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MOTOROLA
Chapter 11
Ethernet Module
This chapter begins with a feature-set overview, a functional block diagram, and transceiver
connection information for both MII and seven-wire serial interfaces. The chapter
concludes with detailed descriptions of operation and the programming model.
11.1 Overview
The MCF5272’s integrated fast Ethernet media access controller (MAC) performs the full
set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface
functions. It requires an external interface adaptor and transceiver function to complete the
interface to the media.
11.1.1 Features
The fast Ethernet controller (FEC) incorporates the following features:
• Full compliance with the IEEE 802.3 standard
• Support for three different physical interfaces:
• Half-duplex 100-Mbps operation at system clock frequency ≥ 50 MHz
• 448 bytes total on-chip transmit and receive FIFO memory to support a range of bus
• Retransmission from transmit FIFO following a collision, no processor bus used
• Automatic internal flushing of the receive FIFO for runts and collisions with no
— 100 Mbps 802.3 media independent interface (MII)
— 10 Mbps 802.3 MII
— 10 Mbps seven-wire interface
latencies
Note: the total FIFO size is 448 bytes. It is not intended to hold entire frames but
only to compensate for external bus latency. The FIFO can be partitioned on any
32-bit boundary between receive and transmit, for example, 32 x 56 receive and
32 x 56 transmit.
processor bus use
Chapter 11. Ethernet Module
11-1
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